Dynamic Nets-to-TSVs Assignment in 3D Floorplanning

We propose a new scheme of dynamic nets-to-TSVs assignment during floorplanning for 3D-ICs. A nontrivial area occupied by TSVs, their physical dimensions, location on the layout and the nets-to-TSVs assignment, are some of the key factors influencing the wirelength, TSV count and chip area, and consequently, impact the total delay. We address the above issues by simultaneous placement of TSV islands with circuit blocks, assignment of nets to TSV islands during floorplanning and directly optimizing interconnect delay. TSVs induce significant thermo-mechanical stress in nearby silicon, and to reduce the impact of stress, we incorporate pitch and Keep-Out-Zone (KOZ) around TSVs in our approach. The proposed dynamic nets-to-TSVs assignment approach, improves solution compared to a previously used fixed nets-to-TSVs assignment, by achieving on average 6-9% delay reduction. Analysis for various TSV aspect ratios using the proposed assignment method is also presented

Nanoelectronics-Beyond CMOS Computing

The six articles in this special section provide a broad perspective on future computing paradigms based on nanoelectronic technology. Nanoelectronics, as the word implies, is literally electronics at the nanoscale, i.e., with characteristic feature sizes less than 50 nm. By most measures, the semiconductor microelectronics industry today is the largest and most successful example of nanoelectronics and nanotechnology in general, where current transistor technology is below 3-nm gate lengths for the most advanced technologies, and the volume of semiconductor industry revenue exceeds US$450 billion. Semiconductor sales, in turn, power portable electronics, personal computers, mainframes, and multiple other industries

Logical Effort Model for CNFET Circuits with CNTs Variations

Carbon Nano-Tube Field Effect Transistors (CNFETs) offer promising solutions beyond conventional CMOS FETs. CNFETs have higher current drive capability, ballistic transport, lesser power delay product and higher thermal stability. The delay evaluation in CNFETs may not be trivial due to additional CNFET specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs that determines current driving capability. Moreover, the initial presence of metallic tubes and their desired removal may result in non-uniform pitch distribution. This random pitch behavior depends on the percentage of metallic tubes and the removal technique deployed. The necessary removal of the metallic tube may have significant impact on the performance of the circuit. In this paper, we propose a closed-form model to capture the impact of metallic tubes and the removal techniques on the gate and circuit delay. The influence of CNT position in the tube array of the gate on the gate-delay is captured in Logical Effort (LE) model. Our model results in fairly accurate delay estimation with an average error 2% - 5% for set of tested CNFET circuits

Polarized Pseudo-Kronecker Symmetry And Synthesis Of 2×2 Lattice Diagrams

This paper proposes new types of symmetries of Boolean functions, and shows how they can be used in a new approach to the important problem of finding variable-expansion orders for lattices. Although this research originates from specific technological considerations, a general problem in functional decomposition is considered: how to decompose a function to a regular structure of simpler functions using symmetries. It has also applications in functional decomposition and Machine Learning. 1 Introductio

Regular realization of symmetric functions using reversible logic

Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little "garbage". Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs